1. Field of the Invention
The present invention relates to a clock multiplier circuit for generating a clock whose frequency is a multiple of a reference clock.
2. Description of the Related Art
In the related art, a PLL (Phase-locked Loop) incorporating a VCO (Voltage-controlled Oscillator) has been used to obtain a clock signal whose frequency is a multiple of a reference clock. FIG. 5 is a block diagram showing the configuration of such a conventional clock multiplier circuit using PLL.
In FIG. 5, a numeral 501 represents a reference clock, 502 a multiple clock output, 511 a phase comparator, 512 a charge pump, 513 a low pass filter, 514 a VCO, 515 a frequency divider, and 516 a waveform shaping circuit.
The reference clock 501 input to the phase comparator 511 is compared with the output of the frequency divider which divides the output of the VCO 514 by N. A control voltage generated by the charge pump 512 and the low pass filter 513 from the phase difference output is supplied to the VCO 514. The control voltage controls the VCO 514 set to oscillate a frequency N times the reference clock 510 for loop control by the PLL. The waveform shaping circuit 516 performs waveform shaping so that the duty cycle of the output waveform of the VCO 514 will be ½.
However, the conventional clock multiplier circuit has two major problems. The first problem is that the low pass filter requires a large time constant in order to stabilize a desired multiple frequency in the conventional clock multiplier circuit. When the low pass filter is built into an LSI, a greater value of a resistor or capacitor as analog devices is required. Due to an increase in the chip size caused by an increase in the footprint of the analog devices or variation in the resistors or capacitors, the PLL could oscillate a signal without locking the phase.
The second problem is that a lock-up time is required to obtain a stable oscillating frequency. FIG. 6 shows the transition in the output frequency of a conventional clock multiplier circuit using a PLL at the start of operation of the output frequency. As shown in FIG. 6, a clock multiplier circuit using a conventional PLL is accompanied by waste of operation time and current consumption before a stable oscillating frequency is obtained.